1. Field of the Disclosure
The invention relates to combinatory logic timing error detection and especially to improvements to subthreshold CMOS devices by a use of a type of new timing error detection circuit.
2. Description of Related Art
In conventional digital design flow, combinational logic delay constraints are static in the sense that the resulting circuit from synthesis must meet the worst case operation condition delays in order to guarantee the circuit operation. If the run-time delay is longer than analyzed during the design time, correct circuit operation cannot be secured. In a conventional design, meeting timing requirements introduces overdesign leading to both area and power—dynamic and static—consumption increase in the system. On the other hand, a timing error detection (TED) system equipped with Error-Detection Sequential (EDS) latches (Bowman, K. A.; et. al. “Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance” IEEE Journal of Solid-State Circuits, Volume: 44, Issue: 1, Page(s): 49-63, 2009) can tolerate late arriving signals from combinational logic. The EDS latch detects late arriving data and reacts to recover from the error. EDS operation is conceptually shown in FIG. 1, where in FIG. 1a a logic stage (102) between two sequential elements (101, 103) is shown. In FIG. 1b, where the signals of the second sequential element (103) are shown, the first transition in D arrives early and does not trigger a conceptual Error signal, whereas the second transition in D arrives late and triggers the Error signal. The Error signal can then be used, for example, to trigger an instruction replay in modern processors. FIG. 2 shows a conventional circuit for error detection, where the data (D) and clock (CLK) inputs of a conventional latch (201) are connected to a transition detector (202) which generates the Error signal when the data transitions within the clock high period (for a positive edge triggered latch).
The minimum energy point for static CMOS logic is in the subthreshold region, where the operating voltage is below the threshold voltage of the CMOS transistors. Although minimum energy operation is achieved, the effect of the variations in modern deep submicron CMOS processes is greatly increased. Subthreshold current is due to diffusion charge transport mechanism and it can be observed that the drain current is exponentially related to the gate-source voltage, drain-source voltage, and thermal voltage. From this exponential relationship it can be seen that, when compared to nominal operating conditions (strong inversion), effects of process variation, supply voltage, and temperature are greatly amplified in the subthreshold operating region.
Combining subthreshold design with TED mitigates the subthreshold design hindrances. Although adding TED circuitry introduces extra energy consumption, the timing error information provided by the TED circuitry can be used to control the circuit operation for better energy efficiency. With TED, circuits can be designed with relaxed timing margin overhead, and dynamic voltage (DVS) or frequency (DFS) scaling can be used alongside error recovery. This works not only from process variance and operating conditions point of view, but a TED system also takes into account data related delay variance issues. However, if the circuits designed for the nominal voltage range are used in the subthreshold range, the size, and thus the energy consumption, of the circuits grows unfeasibly large (Turnquist, M. J.; et. al. “Adaptive Sub-Threshold Test Circuit” NASA/ESA Conference on Adaptive Hardware and Systems, 2009. Page(s): 197-203, 2009).
Subthreshold source-coupled logic (STSCL) can be used to provide both robustness to process, supply voltage and temperature (PVT) variations and reduced power consumption in subthreshold. STSCL has been shown to consume less power than static CMOS for low operation frequencies. Since the delay of an STSCL gate is independent of the threshold voltage (VT), STSCL is more robust to PVT than static CMOS. In addition, STSCL allows for accurate control of gate current consumption and operation frequency. These advantages are all beneficial for TED systems operating in subthreshold where less power overhead, robustness, and ease in adaptability are considered key parameters. As shown in FIG. 3, an STSCL circuit is constructed by a network of differential NMOS pairs comprised of transistors M1,M2 (301), an adjustable PMOS load, transistors M3, M4, (302) with have an output resistance RP, and an adjustable tail current ISS. The NMOS pairs are used to construct logic gates and thus steer ISS between the two PMOS loads. The voltage swing VSW=RP·ISS in STSCL is maintained by balancing the size of RP and magnitude of ISS. Since ISS can be reduced to the pA range in subthreshold, RP needs to be in the low GΩ range to achieve proper VSW. By connecting the bulk of the PMOS load devices to the drain, a large RP is achieved without excessively large transistor lengths. The size of RP and the magnitude of ISS are both adjusted by the Voltage Swing Control (VSC) block (303). The VSC decreases the dependence on global process variations, supply noise, and temperature fluctuations. It is important to recognize that one VSC generates VP and VN for a large number of STSCL gates. The VSC typically consists of an operational amplifier connected to a dummy STSCL circuit.
Error detection principle and error discovery is described in US 2010/079,184 (A1) now U.S. Pat. No. 8,301,970, and in WO2004084072. The general ideas of timing error detection and recovery are not described here in detail. Current mode logic circuits are described in US2009/219,054 (A1)now abandoned.